1. Field of the Invention
The present invention relates to a static random access memory (SRAM) and more particularly to a MOS type SRAM having a voltage stress test circuit for performing a screening test of an initial defective mode due to a voltage acceleration.
2. Description of the Related Art
In general, when the semiconductor devices are manufactured and shipped, a screening test for exposing potential defectiveness of the device and removing the defective device in order to prevent the good devices from being deteriorated and ensure high reliability of the devices. As a screening method, there is often used a burn-in method, which can realize an electrical field acceleration and a temperature acceleration at the same time. In the burn-in method, the device is operated in a state that a voltage is set to be higher than the voltage, which is actually used, and temperature is set to be higher than the temperature, which is actually used. As a result, stress, which is higher than stress for a period of time of an initial trouble in a condition of the actual use, can be applied on the device in a short period of time. Thereby, a certain device having a possibility in which the initial operation trouble will occur is selected before shipping and screened. As a result, the device having a possibility in which the initial operation trouble will occur can be effectively removed and reliability of the device can be improved.
The initial trouble of the semiconductor memory occurs mainly in memory cells. This is because the memory cells occupy substantially all the number of elements on the memory. Moreover, since working in the memory cells is the finest and the memory cells are sensitive to the defective.
Particularly, in order to screen deterioration of a gate oxidation film of a MOS FET having a relatively high frequency of generating troubles in the memory cell, it is required that high voltage stress be applied between both ends of the gate oxidation film. Moreover, in order to screen defective leak current of an impurity diffusion region in the memory cell, it is required that high voltage stress is applied between a reverse-biased pn junction between the diffusion region and a semiconductor substrate.
The following explains the case in which the above-mentioned burn-in process is applied to a SRAM using SRAM cells shown in FIG. 1.
In FIG. 1, NMOS transistors Q1, Q2 and resistors R1, R2 constitute a flip-flop circuit. Q3 and Q4 are NMOS transistors for a transfer gate, and each end of the respective transistors Q3 and Q4 is connected to a pair of bit lines BL, /BL, and each gate thereof is connected to a word line WL.
Voltage stress is applied to the transfer gates Q3 and Q4 of the memory cell during only the time when the word line WL is selected. Moreover, inner nodes N1 and N2 for retaining storage data of the memory cell are connected to a power voltage VCC via high resistors R1 and R2. Due to this, voltage stress is applied to the diffusion region, which constitutes the inner nodes N1 and N2, and the gate oxide film of each of the driving transistors Q1 and Q2 for the period of time of 1/2 the whole test (that is, for the period of time when data "1" or "0" is supplied).
However, in recent years, the SRAM cells are designed such that the values of high resistors R1 and R2 are set to about lTO in order to reduce stand-by power consumption to several .mu.A. Due to this, even if a little leak current starts to flow at the time when voltage stress is applied to the inner nodes N1 and N2 via high resistors R1 and R2, the voltages of the inner nodes N1 and N2 decrease and sufficient stress may not be applied to these nodes.
From the above-mentioned points, it can be considered that the voltage stress actually is applied to the inner nodes N1 and N2 during only the time when the word line WL is selected.
Regarding the burn-in of SRAM, there is conventionally used a method in which the word lines are scanned in order of address and assessed sequentially. Due to this, voltage stress is applied to the SRAM cell with the frequency, which is much smaller than that of the transistors of the peripheral circuits. This will be explained by use of 1M bit SRAM in which 64 cells are connected to one word line as follows.
For example, while the burn-in process is performed for 100 hours, actual time for applying stress to one cell is only about 6 seconds (as shown in the following calculation below) if stress is applied during only the time when the word line WL is selected. EQU 100.times.60.times.60.times.(2.sup.5 /2.sup.20).times.(1/2)=6
The above time is stress applying time to the transfer gates Q3 and Q4. Stress applying time to the driving transistors Q1 and Q2 is haft of time is stress applying time to the transfer gates Q3 and Q4. Actually, the word line is selected during only the partial time of one memory cycle.
As mentioned above, stress applying time per one memory cell is 1/10.sup.10 of the testing time. If voltage stress, which is necessary for screening the initial trouble, is to be applied, burn-in time is considerably prolonged non-efficiently, and manufacturing cost of the memory is increased.
In order to solve the above-mentioned problems and extremely improve the efficiency of screening the defective device, one of inventors, who are inventors of the present invention, proposed a semiconductor memory in published Unexamined Japanese Patent Application (Kokai) No. 3-35491 T.FURUYAMA, which corresponds to U.S. application Ser. No. 07/544,614. In this semiconductor memory, voltage stress is simultaneously applied to all word lines or the word lines, which is more than the number of word lines selected at the time of a normal operation of the memory.
In the SRAM, cell arrays are divided into a plurality of blocks and cell current flows to a pair of bit lines of only the block to which the selected cell belongs at the time of the normal operation. However, if all word lines are selected in a state that an operation power is supplied to the memory at the time of screening the defectiveness, a cell current flows to all pairs of bit lines. Due to this, the total bit line current at the time of screening the defectiveness becomes several tens times at the normal operation, so that there is a possibility that the operation fault of SRAM will occur.
Moreover, voltage stress is preferably applied to not only the transfer gates but also the driving transistors in applying voltage stress to the memory cell of SRAM.